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general description the MAX3798 is a highly integrated limiting amplifier and vcsel driver designed for 1x/2x/4x/8x fibre channel transmission systems at data rates up to 8.5gbps as well as for 10gbase-sr transmission sys- tems at a data rate of 10.3125gbps. operating from a single +3.3v supply, this low-power integrated limiting amplifier and vcsel driver ic enables a platform design for sfp msa as well as for sfp+ msa-based optical transceivers. the high-sensitivity limiting ampli- fier limits the differential input signal generated by a transimpedance amplifier into a cml-level differential output signal. the compact vcsel driver provides a modulation and a bias current for a vcsel diode. the optical average power is controlled by an average power control (apc) loop implemented by a controller that interfaces to the vcsel driver through a 3-wire digital interface. all differential i/os are optimally back- terminated for a 50 transmission line pcb design. the use of a 3-wire digital interface reduces the pin count while enabling advanced rx (mode selection, los threshold, los squelch, los polarity, cml output level, signal path polarity, slew-rate control, deempha- sis, and fast mode-select change time) and tx settings (modulation current, bias current, polarity, programma- ble deemphasis, eye-crossing adjustment, and eye safety control) without the need for external compo- nents. the MAX3798 provides multiple current and volt- age dacs to allow the use of low-cost controller ics. the MAX3798 is packaged in a lead-free, 5mm x 5mm, 32-pin tqfn package. applications 10gbase-sr sfp+ optical transceiver 1x/2x/4x/8x sff/sfp/sfp+ msa fibre channel (fc) optical transceiver 10gbase-lr sfp+ optical transceiver (1310nm vcsel) 10gbase-lrm sfp+ optical transceiver (1310nm vcsel) features ? low power dissipation of 320mw at 3.3v power supply ? up to 10.32gbps (nrz) operation ? 3mv p-p receiver sensitivity at 10.32gbps ? 4ps p-p dj at receiver output at 8.5gbps 8b/10b ? 4ps p-p dj at receiver output at 10.32gbps 2 31 - 1 prbs ? 26ps rise and fall time at rx/tx output ? mode select for high-gain mode and high- bandwidth mode ? cml output slew-rate adjustment for high-gain mode ? cml output with continuous level adjustment ? cml output squelch ? polarity select for rx and tx ? los assert level adjustment ? los polarity select ? modulation current up to 12ma into 100 differential load ? bias current up to 15ma ? integrated eye safety features ? selectable deemphasis at rx output ? 3-wire digital interface ? eye-crossing adjustment of modulation output ? programmable deemphasis at tx output ? fast mode-select change time of 10? MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ________________________________________________________________ maxim integrated products 1 ordering information 19-4360; rev 0; 10/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX3798etj+ -40 c to +85 c 32 tqfn-ep* typical application circuit and pin configuration appear at end of data sheet.
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v ccr , v cct , v ccd .................................................-0.3v to +4.0v voltage range at disable, sda, scl, csel, msel, fault, bmon, los, bmax, mmax, caz2...............................-0.3v to (v cc + 0.3v) voltage range at rout+, rout- .....(v cc - 1v) to (v cc + 0.3v) voltage at tin+, tin-........................(v cc - 2.5v) to (v cc - 0.5v) voltage range at tout+, tout- ......(v cc - 2v) to (v cc + 0.3v) voltage at bias...............................................................0 to v cc voltage at rin+, rin- ..........................(v cc - 2v) to (v cc - 0.2v) current range into fault, los...........................-1ma to +5ma current range into sda........................................-1ma to +1ma current into rout+, rout- ...............................................40ma current into tout+, tout- ................................................60ma continuous power dissipation (t a = +70 c) 32-pin tqfn (derate 34.5w/c above +70c) ...........2759mw operating junction temperature range ...........-55c to +150c storage temperature range .............................-65c to +160c parameter symbol conditions min typ max units power supply power-supply current i cc includes the cml output current; excludes i bias = 6ma, i mod = 6ma, v diff_rout = 400mv p-p (note 1) 97 150 ma power-supply voltage v cc 2.85 3.63 v general input data rate 1.0625 10.32 gbps input/output snr 14.1 ber 10e-12 power-on reset high por threshold 2.55 2.75 v low por threshold i bias = i biasoff and i mod = i modoff 2.3 2.45 v rx input specifications differential input resistance rin+/rin- r in_diff 75 100 125 mode_sel = 0 at 4.25gbps 2 4 input sensitivity (note 2) v inmin mode_sel = 1 at 8.5gbps 3 8 mv p-p input overload v inmax 1.2 v p-p dut is powered on, f 5ghz 14 input return loss sdd11 dut is powered on, f 16ghz 7 db dut is powered on, 1ghz < f 5ghz 8 input return loss scc11 dut is powered on, 1ghz < f 16ghz 8 db rx output specifications differential output resistance r outdiff 75 100 125 dut is powered on, f 5ghz 11 output return loss sdd22 dut is powered on, f 16ghz 5 db
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) parameter symbol conditions min typ max units dut is powered on, 1ghz < f 5ghz 9 output return loss scc22 dut is powered on, 1ghz < f 16ghz 7 db cml differential output voltage high 5mv p-p v in 1200mv p-p , set_cml[162] 595 800 1005 mv p-p cml differential output voltage medium 10mv p-p v in 1200mv p-p , set_cml[80] 300 400 515 mv p-p differential output signal when disabled outputs ac-coupled, v inmax applied to input v diff_rout = 800mv p-p at 8.5gbps (notes 2, 3) 6 15 mv p-p 10mv p-p v in 1200mv p-p , mode_sel = 1, v diff_rout = 400mv p-p 26 35 5mv p-p v in 1200mv p-p , mode_sel = 0, slew_rate = 1, v diff_rout = 800mv p-p 28 50 data output transition time (20% to 80%) (notes 2, 3, 4) t r /t f 5mv p-p v in 1200mv p-p , mode_sel = 0, slew_rate = 0, v diff_rout = 800mv p-p 45 ps rx transfer characteristics 60mv p-p v in 400mv p-p at 10.32gbps, mode_sel = 1, v diff_rout = 400mv p-p 4 12 10mv p-p v in 1200mv p-p at 8.5gbps, mode _sel = 1, v diff_rout = 400mv p-p 4 12 10mv p-p v in 1200mv p-p at 4.25gbps, mode _sel = 1, v diff_rout = 400mv p-p 5 10mv p-p v in 1200mv p-p at 8.5gbps, mode _sel = 0, v diff_rout = 400mv p-p 5 10 5mv p-p v in 1200mv p-p at 4.25gbps, mode _sel = 0, slew_rate = 1, v diff_rout = 800mv p-p 6 20 deterministic jitter (notes 2, 3, 5) dj 5mv p-p v in 1200mv p-p at 4.25gbps, mode _sel = 0, slew_rate = 0, v diff_rout = 800mv p-p 7 ps p-p input = 60mv p-p at 4.25gbps , mode_sel = 0, v diff_rout = 800mv p-p 0.36 0.51 random jitter (notes 2, 3) rj input = 60mv p-p at 8.5gbps , mode _sel = 1, v diff_rout = 400mv p-p 0.32 0.48 ps rms c az = 0.1f 2 low-frequency cutoff c az = open 500 khz rx los specifications los assert sensitivity range 14 77 mv p-p los hysteresis 10 x log (v deassert /v assert ) (note 6) 1.25 2.1 db
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) parameter symbol conditions min typ max units los assert/deassert time (note 7) 2.3 80 s low assert level set_los[7] (notes 2, 6) 8 11 14 mv p-p low deassert level set_los[7] (notes 2, 6) 14 18 21 mv p-p medium assert level set_los[32] (notes 2, 6) 39 48 58 mv p-p medium deassert level set_los[32] (notes 2, 6) 65 81 95 mv p-p high assert level set_los[63] (notes 2, 6) 77 94 112 mv p-p high deassert level set_los[63] (notes 2, 6) 127 158 182 mv p-p tx input specifications data rate = 1.0625gbps to 4.25gbps 0.2 2.4 differential input voltage v in data rate = 4.25gbps to 10.32gbps 0.075 0.8 v p-p common-mode input voltage v incm 2.75 v differential input resistance r in 75 100 125 dut is powered on, f 5ghz 15 input return loss sdd11 dut is powered on, f 16ghz 6 db dut is powered on, 1ghz < f 5ghz 9 input return loss scc11 dut is powered on, 1ghz < f 16ghz 5 db tx laser modulator maximum modulation-on current into 100 differential load i modmax outputs ac-coupled, v ccto 2.95v 12 ma minimum modulation-on current into 100 differential load i modmin outputs ac-coupled 2 ma modulation current dac stability 2ma i mod 12ma (note 8) 4 % modulation current rise time/ fall time t r /t f 5ma i mod 10ma, 20% to 80%, set_txde[3:0] = 10 (notes 2, 4) 26 39 ps 5ma i mod 12ma, at 10.32gbps, 250mv p-p v in 800mv p-p , set_txde[4:1] = 0 6 12 5ma i mod 12ma, at 10.32gbps, 250mv p-p v in 800mv p-p , set_txde[4:1] = 10 6 13 5ma i mod 12ma, at 8.5gbps, 250mv p-p v in 800mv p-p , set_txde[4:1] = 0 6 12 5ma i mod 12ma, at 8.5gbps, 250mv p-p v in 800mv p-p , set_txde[4:1] = 10 6 12 2ma i mod 12ma, at 4.25gbps 5 deterministic jitter (notes 2, 9) dj 2ma i mod 12ma, at 1.0625gbps 5 ps
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver _______________________________________________________________________________________ 5 electrical characteristics (continued) (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) parameter symbol conditions min typ max units random jitter 5ma i mod 12ma, 250mv p-p v in 800mv p-p 0.17 0.5 ps rms dut is powered on, f 5ghz 12 output return loss sdd22 dut is powered on, f 16ghz 5 db tx bias generator maximum bias-on current i biasmax current into bias pin 15 ma minimum bias-on current i biasmin current into bias pin 2 ma bias current dac stability 2ma i bias 15ma (notes 2, 10) 4 % compliance voltage at bias v bias 0.9 2.1 v bias current monitor current gain i bmon external resistor to gnd defines the voltage gain 16 ma/a compliance voltage at bmon v bmon 0 1.8 v bias current monitor current gain stability i bmon 2ma i bias 15ma (note 10) 5 % tx safety features excessive voltage at bmax v bmax average voltage, fault always occurs for v bmax v cc - 0.65v, fault never occurs for v bmax v cc - 0.55v v cc - 0.65v v cc - 0.6v v cc - 0.55v v excessive voltage at mmax v mmax average voltage, fault always occurs for v mmax v cc - 0.65v, fault never occurs for v mmax v cc - 0.55v v cc - 0.65v v cc - 0.6v v cc - 0.55v v excessive voltage at bmon v bmon average voltage, fault warning always occurs for v bmon v cc - 0.55v, fault warning never occurs for v bmon v cc - 0.65v v cc - 0.65v v cc - 0.6v v cc - 0.55v v excessive voltage at bias v bias average voltage, fault always occurs for v bias 0.44v, fault never occurs for v bias 0.65v 0.44 0.48 0.65 v maximum vcsel current in off state i off fault or disable, v bias = v cc 25 a sfp timing requirements mode-select change time t_ modesel time from rising or falling edge at msel until rx output pwd falls below 10ps 10 s disable assert time t_ off time from rising edge of disable input signal to i bias = i biasoff and i mod = i modoff 1 s
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 6 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) parameter symbol conditions min typ max units disable negate time t_ on time from falling edge of disable to i bias and i mod at 90% of steady state when fault = 0 before reset 500 s fault reset time of power-on time t_ init time from power-on or negation of fault using disable 100 ms fault reset time t_ fault time from fault to fault on, c fault 20pf, r fault = 4.7k 10 s disable to reset time disable must be held high to reset fault 5 s output level voltage dac (set_cml) full-scale voltage v fs 100 differential resistive load 1200 mv p-p resolution 5 mv p-p integral nonlinearity inl 5ma i cml_level 20ma 0.9 lsb los threshold voltage dac (set_los) full-scale voltage v fs 94 mv p-p resolution 1.5 mv p-p integral nonlinearity inl 11mv p-p v th_los 94mv p-p 0.7 lsb bias current dac (set_ibias) full-scale current i fs 21 ma resolution 40 a integral nonlinearity inl 1ma i bias 15ma 1 lsb differential nonlinearity dnl 1ma i bias 15ma, guaranteed mono- tonic at 8-bit resolution (set_ibias[8:1]) 1 lsb modulation current dac (set_imod) full-scale current i fs 21 ma resolution 40 a integral nonlinearity inl 2ma i mod 12ma 1 lsb differential nonlinearity dnl 2ma i mod 12ma, guaranteed mono- tonic at 8-bit resolution (set_imod[8:1]) 1 lsb control i/o specifications msel input current i ih , i il 150 a msel input high voltage v ih 1.8 v cc v msel input low voltage v il 0 0.8 v msel input impedance r pull internal pulldown resistor 40 75 110 k i ih 12 disable input current i il dependency on pullup resistance 420 800 a disable input high voltage v ih 1.8 v cc v
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver _______________________________________________________________________________________ 7 electrical characteristics (continued) (v cc = 2.85v to 3.63v, t a = -40c to +85c, cml receiver output load is ac-coupled to differential 100 , c az = 1nf, transmitter out- put load is ac-coupled to differential 100 (see figure 1), typical values are at +25c, v cc = 3.3v, i bias = 6ma, i mod = 6ma, unless otherwise specified. registers are set to default values unless otherwise noted, and the 3-wire interface is static during meas ure- ments. for testing, the mode_sel bit was used and the msel pin was left open.) parameter symbol conditions min typ max units disable input low voltage v il 0 0.8 v disable input impedance r pull internal pullup resistor 5.5 8 10.5 k los, fault output high voltage v oh r los = 4.7k - 10k to v cc , r fault = 4.7k - 10k to v cc v cc - 0.5 v cc v los, fault output low voltage v ol r los = 4.7k - 10k to v cc , r fault = 4.7k - 10k to v cc 0 0.4 v 3-wire digital i/o specifications (sda, csel, scl) input high voltage v ih 2.0 v cc v input low voltage v il 0.8 v input hysteresis v hyst 0.082 v input leakage current i il , i ih v in = 0v or v cc ; internal pullup or pulldown (75k typical) 150 a output high voltage v oh external pullup of 4.7k to v cc v cc - 0.5 v output low voltage v ol external pullup of 4.7k to v cc 0.4 v 3-wire digital interface timing characteristics (see figure 4) scl clock frequency f scl 400 1000 khz scl pulse-width high t ch 0.5 s scl pulse-width low t cl 0.5 s sda setup time t ds 100 ns sda hold time t dh 100 ns scl rise to sda propagation time t d 5ns csel pulse-width low t csw 500 ns csel leading time before the first scl edge t l 500 ns csel trailing time after the last scl edge t t 500 ns sda, scl external load c b total bus capacitance on one line with 4.7k pullup to v cc 20 pf note 1: supply current is measured with unterminated receiver cml output or with ac-coupled rx output termination. the tx out- put and the bias current output must be connected to a separate supply in order to remove the modulation/bias current portion from the supply current. bias must be connected to 2.0v. tout+/- must be connected through 50 load resistors to a separate supply voltage. note 2: guaranteed by design and characterization, t a = -40c to +95c. note 3: the data input transition time is controlled by a 4th-order bessel filter with -3db frequency = 0.75 x data rate. the determin- istic jitter caused by this filter is not included in the dj generation specifications. note 4: test pattern is 00001111 at 4.25gbps for mode_sel = 0. test pattern is 00001111 at 8.5gbps for mode_sel = 1.
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 8 _______________________________________________________________________________________ MAX3798 v ccr los msel rout+ disable v ccd v eer bmax v eet fault tout+ v cct bias 1nf 0.1 f 0.1 f 1000pf 50 50 4.7k 400 4.7k 400 1k 1000pf 1 h v cc v ccr v cct v ccd 0.1 f 0.1 f v ccr v cct v cct v ccd 1000pf v cct oscilloscope v ccr controller controller controller controller 50 50 50 rout- 0.1 f 50 50 scl sda csel tin+ 0.1 f 50 tin- bmon caz1 caz2 rin+ 0.1 f 50 rin- mmax tout- 0.1 f 50 oscilloscope 50 50 0.1 f 0.1 f figure 1. test circuit for vcsel driver characterization note 5: receiver deterministic jitter is measured with a repeating 2 31 - 1 prbs equivalent pattern at 10.32gbps. for 1.0625gbps to 8.5gbps, a repeating k28.5 pattern [00111110101100000101] is used. deterministic jitter is defined as the arithmetic sum of pulse-width distortion (pwd) and pattern-dependent jitter (pdj). note 6: measured with a k28.5 pattern from 1.0625gbps to 8.5gbps. measured with 2 31 - 1 prbs at 10.32gbps. note 7: measurement includes an input ac-coupling capacitor of 100nf and c caz of 100nf. the signal at the input is switched between two amplitudes: signal_on and signal_off. 1) receiver operates at sensitivity level plus 1db power penalty. a) signal_off = 0 signal_on = (+8db) + 10log(min_assert_level) b) signal_on = (+1db) + 10log(max_deassert_level) signal_off = 0 2) receiver operates at overload. signal_off = 0 signal_on = 1.2v p-p max_deassert_level and the min_assert_level are measured for one los_threshold setting. note 8: gain stability is defined as [(i_measured) - (i_reference)]/(i_reference) over the listed current range, temperature, and v cc from +2.95v to +3.63v. reference current measured at v cc = +3.2v, t a = +25c. note 9: transmitter deterministic jitter is measured with a repeating 2 7 - 1 prbs, 72 0s, 2 7 - 1 prbs, and 72 1s pattern at 10.32gbps. for 1.0625gbps to 8.5gbps, a repeating k28.5 pattern [00111110101100000101] is used. deterministic jitter is defined as the arithmetic sum of pwd and pdj. note 10: gain stability is defined as [(i_measured) - (i_reference)]/(i_reference) over the listed current range, temperature, and v cc from +2.85v to +3.63v. reference current measured at v cc = +3.3v, t a = +25c.
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver _______________________________________________________________________________________ 9 random jitter vs. input amplitude MAX3798 toc01 input amplitude (mv p-p ) random jitter (ps) 1000 800 600 400 200 310 320 330 340 350 360 370 300 0 1200 at 4.25gbps mode_sel = 0 at 8.5gbps mode_sel = 1 deterministic jitter vs. input amplitude at 4.25gbps MAX3798 toc02 input amplitude (mv p-p ) deterministic jitter (ps) 1000 800 600 400 200 4 5 6 7 8 9 10 11 12 3 0 1200 pattern = k28.5, mode_select = 0 slew_rate = 0 slew_rate = 1 deterministic jitter vs. input amplitude MAX3798 toc03 input amplitude (mv p-p ) deterministic jitter (ps) 1000 800 600 400 200 2 3 4 5 6 7 1 0 1200 pattern = prbs, mode_sel = 1 at 8.5gbps at 10.32gbps deterministic jitter vs. data rate MAX3798 toc04 data rate (gbps) deterministic jitter (ps) 10 8 2 4 6 3 4 5 6 7 8 9 10 2 012 pattern = k28.5 mode_sel = 0, slew_rate = 1 mode_sel = 1 ber vs. input amplitude input amplitude (mv p-p ) ber 2.0 1.5 1.0 1.0e-08 1.0e-09 1.0e-10 1.0e-07 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e-11 0.5 2.5 MAX3798 toc05 at 8.5gbps mode_sel = 0 at 8.5gbps mode_sel = 1 output eye diagram at 10.32gbps MAX3798 toc06 20ps/div 50mv/div output eye diagram at 8.5gbps MAX3798 toc07 20ps/div 50mv/div output eye diagram at 4.25gbps MAX3798 toc08 50ps/div 50mv/div mode_sel = 1 output eye diagram at 4.25gbps MAX3798 toc09 50ps/div 100mv/div mode_sel = 0, slew_rate = 1 typical operating characteristics?imiting amplifier (v cc = 3.3v, t a = +25c, unless otherwise specified. figure 1 shows the typical setup used for measurements. registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. for testing, the mode_sel bit wa s used and the msel pin was left open.)
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 10 ______________________________________________________________________________________ output eye diagram at 4.25gbps MAX3798 toc10 50ps/div 100mv/div mode_sel = 0, slew_rate = 0 transition time vs. input amplitude MAX3798 toc11 input amplitude (mv p-p ) transition time (ps) 1000 800 600 400 200 5 10 15 20 25 30 35 40 45 50 0 0 1200 mode_sel = 0, slew_rate = 0, rxde_en = 0 mode_sel = 0, slew_rate = 0, rxde_en = 1 mode_sel = x, slew_rate = 1, rxde_en = 1 mode_sel = x, slew_rate = 1, rxde_en = 0 pattern = 00001111, data rate = 8.5gbps, 20% to 80% los threshold vs. dac setting MAX3798 toc12 set_los[5:0] los threshold (mv) 56 49 35 42 14 21 28 7 20 40 60 80 100 120 140 160 180 0 063 deassert assert sensitivity vs. data rate MAX3798 toc13 data rate (gbps) sensitivity oma (dbm) 10 8 6 4 -17 -16 -15 -14 -13 -12 -18 212 using finisar rosa mode_sel = 1 mode_sel = 0 rx input return loss MAX3798 toc14 frequency (hz) sdd11 (db) 10g 1g -50 -40 -30 -20 -10 0 -60 100m 100g rx output return loss MAX3798 toc15 frequency (hz) sdd22 (db) 10g 1g -45 -40 -35 -30 -25 -20 -15 -10 -5 0 -50 100m 100g cml output amplitude vs. dac setting MAX3798 toc16 set_cml[7:0] cml output amplitude (mv p-p ) 250 200 150 100 50 200 400 600 800 1000 1200 1400 0 0 300 typical operating characteristics?imiting amplifier (continued) (v cc = 3.3v, t a = +25c, unless otherwise specified. figure 1 shows the typical setup used for measurements. registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. for testing, the mode_sel bit wa s used and the msel pin was left open.)
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 11 typical operating characteristics?csel driver (v cc = 3.3v, t a = +25c, unless otherwise specified. figure 1 shows the typical setup used for measurements. registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. for testing, the mode_sel bit wa s used and the msel pin was left open.) total supply current vs. temperature MAX3798 toc17 temperature ( c) supply current (ma) 80 65 35 50 -10 5 20 -25 50 60 70 80 90 100 110 120 130 140 40 -40 95 i bias = 12ma i bias = 9ma i bias = 2ma i mod = 2ma; receiver output = 400mv p-p ; total supply measured using the setup in figure 1. total supply current vs. temperature MAX3798 toc18 temperature ( c) supply current (ma) 80 65 35 50 -10 5 20 -25 50 60 70 80 90 100 110 120 130 140 150 160 40 -40 95 i mod = 12ma i mod = 9ma i mod = 2ma i bias = 2ma; receiver output = 400mv p-p ; total supply measured using the setup in figure 1. optical eye diagram MAX3798 toc19 14ps/div 10.3gbps, set_imod = 60, 2 7 - 1 prbs, 850nm vcsel, mask with 44% optical eye diagram MAX3798 toc20 17ps/div 8.5gbps, set_imod = 60, 2 7 - 1 prbs, 850nm vcsel, mask with 54% optical eye diagram MAX3798 toc21 34ps/div 4.25gbps, set_imod = 60, 2 7 - 1 prbs, 850nm vcsel, mask with 46% optical eye diagram MAX3798 toc22 68ps/div 2.125gbps, set_imod = 60, 2 7 - 1 prbs, 850nm vcsel, mask with 50% deterministic jitter vs. modulation current MAX3798 toc23 modulation current (ma p-p ) deterministic jitter (ps) 10 8 6 4 5.0 5.5 6.0 6.5 7.0 7.5 8.0 4.5 212 pattern = prbs, data rate = 10.32gbps transition time vs. modulation current MAX3798 toc24 modulation current (ma p-p ) transition time (ps) 10 8 6 4 8 13 18 23 28 33 38 3 212 fall time rise time pattern = 11110000, data rate = 8.5gbps transition time vs. deemphasis setting MAX3798 toc25 set_txde[3:0] transition time (ps) 10 9 1 2 3 5 6 7 4 8 27 29 31 33 35 37 39 41 25 011 fall time rise time pattern = 11110000, data rate = 8.5gbps, i mod = 10ma p-p
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 12 ______________________________________________________________________________________ typical operating characteristics?csel driver (continued) (v cc = 3.3v, t a = +25c, unless otherwise specified. figure 1 shows the typical setup used for measurements. registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. for testing, the mode_sel bit wa s used and the msel pin was left open.) modulation current vs. dac setting MAX3798 toc26 set_imod[8:0] modulation current (ma) 250 200 150 100 50 2 4 6 8 10 12 14 0 0 300 r load = 50 r load = 75 r load = 100 bias current vs. dac setting MAX3798 toc27 set_ibias[8:0] bias current (ma) 250 200 150 100 50 2 4 6 8 10 12 14 0 0 300 transmitter disable MAX3798 toc28 100ns/div v cc fault disable output low low high 3.3v transmitter enable MAX3798 toc29 1 s/div v cc fault disable output low low high 3.3v t on = 420ns response to fault MAX3798 toc30 1 s/div v bias fault disable output low low high externally forced fault fault recovery MAX3798 toc31 4 s/div v bias fault disable output low low high external fault high frequency assertion of disable MAX3798 toc32 4 s/div v bias fault disable output low low high high externally forced fault tx input return loss MAX3798 toc33 frequency (hz) sdd11 (db) 10g 1g -50 -40 -30 -20 -10 0 -60 100m 100g tx output return loss MAX3798 toc34 frequency (hz) sdd22 (db) 10g 1g -40 -35 -30 -25 -20 -15 -10 -5 0 -45 100m 100g
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 13 pin description pin name function 1 los loss-of-signal output, open drain. the default polarity of los is high when the level of the input signal is below the preset threshold set by the set_los dac. polarity of the los function can be inverted by setting los_pol = 0. the los circuitry can be disabled by setting the bit los_en = 0. 2 msel mode-select input, ttl/cmos. set the msel pin or mode_sel bit (set by the 3-wire digital interface) to logic-high for high-bandwidth mode. setting msel and mode_sel logic-low for high-gain mode. the msel pin is internally pulled down by a 75k resistor to ground. 3, 6, 27, 30 v ccr power supply. provides supply voltage to the receiver block. 4 rout+ noninverted receive data output, cml. back-terminated for 50 load. 5 rout- inverted receive data output, cml. back-terminated for 50 load. 7 v ccd power supply. provides supply voltage for the digital block. 8 disable transmitter disable input, ttl/cmos. set to logic-low for normal operation. logic-high or open disables both the modulation and bias current. internally pulled up by an 8k resistor to v cc . 9 scl serial clock input, ttl/cmos. this pin has a 75k internal pulldown. 10 sda serial data bidirectional input, ttl/cmos. open-drain output. this pin has a 75k internal pullup, but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (data line collision protection is implemented.) 11 csel chip-select input, ttl/cmos. setting csel to logic-high starts a cycle. setting csel to logic-low ends the cycle and resets the control state machine. internally pulled down by a 75k resistor to ground. 12, 15, 18, 21 v cct power supply. provides supply voltage to the transmitter block. 13 tin+ noninverted transmit data input, cml typical operating characteristics?csel driver (continued) (v cc = 3.3v, t a = +25c, unless otherwise specified. figure 1 shows the typical setup used for measurements. registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. for testing, the mode_sel bit wa s used and the msel pin was left open.) deterministic jitter vs. pulse-width setting MAX3798 toc35 set_pwctrl[3:0] deterministic jitter (ps) 5 3 -5 -3 -1 1 3 4 5 6 7 8 9 10 2 -7 7 pattern = prbs, data rate = 10.32gbps eye crossing down up bias monitor current vs. temperature MAX3798 toc36 temperature ( c) monitor current ( a) 80 65 -25 -10 5 35 20 50 100 200 300 400 500 600 700 800 0 -40 95 i bias = 12ma i bias = 8ma i bias = 2ma
MAX3798 detail description the MAX3798 sfp+ transceiver combines a limiting amplifier receiver with loss-of-signal detection and a vcsel laser driver transmitter with fault protection. configuration of the advanced rx and tx settings of the MAX3798 is performed by a controller through the 3-wire interface. the MAX3798 provides multiple cur- rent and voltage dacs to allow the use of low-cost con- troller ics. limiting amplifier receiver the limiting amplifier receiver inside the MAX3798 is designed to operate from 1.0625gbps to 10.32gbps. the receiver includes a dual path limiter, offset correc- tion circuitry, cml output stage with deemphasis, and loss-of-signal circuitry. the functions of the receiver can be controlled through the on-chip 3-wire interface. the registers that control the receiver functionality are rxctrl1, rxctrl2, rxstat, modectrl, set_cml, and set_los. 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 14 ______________________________________________________________________________________ pin description (continued) pin name function 14 tin- inverted transmit data input, cml 16 bmon bias current monitor output. current out of this pin develops a ground-referenced voltage across an external resistor that is proportional to the laser bias current. 17 v eet ground. provides ground for the transmitter block. 19 tout- inverted modulation current output. back-termination of 50 to v cct . 20 tout+ noninverted modulation current output. back-termination of 50 to v cct . 22 bias vcsel bias current output 23 fault transmitter fault output, open drain. logic-high indicates a fault condition. fault remains high even after the fault condition has been removed. a logic-low occurs when the fault condition has been removed and the fault latch has been cleared by the disable signal. 24 bmax analog vcsel bias current limit. a resistor connected between bmax and v cct sets the maximum allowed vcsel bias current. 25 mmax analog vcsel modulation current limit. a resistor connected between mmax and v cct sets the maximum allowed vcsel modulation current. 26 v eer ground. provides ground for the receiver block. 28 rin- inverted receive data input, cml 29 rin+ noninverted receive data input, cml 31 caz2 offset correction loop capacitor. a capacitor connected between this pin and caz1 sets the time constant of the offset correction loop. the offset correction can be disabled through the digital interface by setting the bit az_en = 0. 32 caz1 offset correction loop capacitor. counterpart to caz2, internally connected to v eer . ep exposed pad. ground. must be soldered to circuit board ground for proper thermal and electrical performance (see the exposed-pad package section).
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 15 r pull r pull r pull r pull v eer v ccd MAX3798 0 1 1 0 1 0 slew-rate control bias monitor output control logic los 3-wire interface control logic pulse- width control i vcsel = i mod - i de internal register offset correction cazx 4b dac set_txde 4b dac set_pwctrl 9b dac set_ibias 9b dac set_imod 8b dac set_cml 6b dac set_los gmen slew_rate rxde_en tx_pol caz1 rin+ msel scl sda csel bias tout+ tout- fault bmax mmax bmon i bias i mod i de rin- caz2 az_en sq_en mode_sel los_en tx_en los_pol rx_pol rout+ rout- los tin+ tin- disable r pull v cct 10.32gbps limiting ampifier 10.32gbps vcsel driver eye safety and output control vcsel bias current limiter vcsel mod current limiter power-on reset figure 2. functional diagram
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 16 ______________________________________________________________________________________ dual path limiter the limiting amplifier features a high-gain mode and a high-bandwidth mode allowing for overall system opti- mization. either the msel pin or the mode_sel bit can perform the mode selection. for operating up to 4.25gbps, the high-gain mode (mode_sel = 0) is rec- ommended. for operating above 8.5gbps, the high- bandwidth mode (mode_sel = 1) is recommended. for operations at 8.5gbps, the mode selection is dependent on the performance of the receiver optical subassembly. the polarity of rout+/rout- relative to rin+/rin- is programmed by the rx_pol bit. offset correction circuitry the offset correction circuit is enabled to remove pulse- width distortion caused by intrinsic offset voltages with- in the differential amplifier stages. an external capacitor (c az ) connected between the caz1 and caz2 pins is used to set the offset correction loop cutoff frequency. the offset loop can be disabled using the az_en bit. the MAX3798 contains a feature that allows the part to meet a 10s mode-select switching time. the mode- select switching time can be adjusted using the gmen and cazx bits. cml output stage with deemphasis and slew-rate control the cml output stage is optimized for differential 100 loads. the rxde_en bit adds analog deemphasis compensation to the limited differential output signal for sfp connector losses. the output stage is controlled by a combination of the rx_en and sq_en bits and the los pin. see table 1. amplitude of the cml output stage is controlled by an 8-bit dac register (set_cml). the differential output amplitude range is from 40mv p-p up to 1200mv p-p with 4.6mv p-p resolution (assuming an ideal 100 differen- tial load). the lower bandwidth data path allows for reduction of output edge speed in order to enhance emi perfor- mance. the slew_rate bit controls the slew rate of the output stage (see table 2). loss-of-signal (los) circuitry the input data amplitude is compared to a preset threshold controlled by the 6-bit dac register set_los. the los assert level can be programmed from 14mv p-p up to 77mv p-p with 1.5mv p-p resolution (assuming an ideal 100 differential source). los is enabled through the los_en bit and the polarity of the los is controlled with the los_pol bit. vcsel driver the vcsel driver inside the MAX3798 is designed to operate from 1.0625gbps to 10.32gbps. the transmit- ter contains a differential data path with pulse-width adjustment, bias current and modulation current dacs, output driver with programmable deemphasis, power- on reset circuitry, bias monitor, vcsel current limiter, and eye safety circuitry. a 3-wire digital interface is used to control the transmitter functions. the registers that control the transmitter functionality are txctrl, txstat1, txstat2, set_ibias, set_imod, imod- max, ibiasmax, modinc, biasinc, modectrl, set_pwctrl, and set_txde. differential data path the cml input buffer is optimized for ac-coupled sig- nals and is internally terminated with a differential 100 . differential input data is equalized for high-frequency losses due to sfp connectors. the tx_pol bit in the txctrl register controls the polarity of tout+ and tout- vs. tin+ and tin-. the set_pwctrl register rx_en sq_en los operation mode description 0 x x cml output disabled. 1 0 x cml output enabled. 1 1 0 cml output enabled. 1 1 1 cml output disabled. table 1. cml output stage operation mode mode_sel slew_rate operation mode description 0 0 4.25gbps operation with reduced output edge speed. 0 1 4.25gbps operation with full edge speed; 8.5gbps operation with high bandwidth rosa. 1 x 8.5gbps with lower bandwidth rosa; 10.32gbps operation. table 2. slew-rate control for cml output stage
controls the output eye-crossing adjustment. a status indicator bit (txed) monitors the presence of an ac input signal. bias current dac the bias current from the MAX3798 is optimized to pro- vide up to 15ma of bias current into a 50 to 75 vcsel load with 40a resolution. the bias current is controlled through the 3-wire digital interface using the set_ibias, ibiasmax, and biasinc registers. for vcsel operation, the ibasmax register is first pro- grammed to a desired maximum bias current value (up to 15ma). the bias current to the vcsel then can range from zero to the value programmed into the ibiasmax register. the bias current level is stored in the 9-bit set_ibias register. only bits 1 to 8 are written to. the lsb (bit 0) of set_ibias is initialized to zero and is updated through the biasinc register. the value of the set_ibias dac register is updated when the biasinc register is addressed through the 3-wire interface. the biasinc register is an 8-bit regis- ter where the first 5 bits contain the increment informa- tion in twos complement notation. increment values range from -8 to +7 lsbs. if the updated value of set_ibias[8:1] exceeds ibiasmax[7:0], the ibiaserr warning flag is set and set_ibias[8:0] remains unchanged. modulation current dac the modulation current from the MAX3798 is optimized to provide up to 12ma of modulation current into a 100 differential load with 40a resolution. the modu- lation current is controlled through the 3-wire digital interface using the set_imod, imodmax, modinc, and set_txde registers. for vcsel operation, the imodmax register is first pro- grammed to a desired maximum modulation current value (up to 12ma into a 100 differential load). the modulation current to the vcsel then can range from zero to the value programmed into the imodmax regis- ter. the modulation current level is stored in the 9-bit set_imod register. only bits 1 to 8 are written to. the lsb (bit 0) of set_imod is initialized to zero and is updated through the modinc register. the value of the set_imod dac register is updated when the modinc register is addressed through the 3-wire interface. the modinc register is an 8-bit regis- ter where the first 5 bits contain the increment informa- tion in twos complement notation. increment values range from -8 to +7 lsbs. if the updated value of set_imod[8:1] exceeds imodmax[7:0], the imoderr warning flag is set and set_imod[8:0] remains unchanged. output driver the output driver is optimized for an ac-coupled 100 differential load. the output stage also features program- mable deemphasis that allows the deemphasis ampli- tude to be set as a percentage of the modulation current. the deemphasis function is enabled by the txde_en bit. at initial setup the required amount of deemphasis can be set using the set_txde register. during the system operation, it is advised to use the incremental mode that updates the deemphasis (set_txde) and the modulation current dac (set_imod) simultaneous- ly through the modinc register. power-on reset (por) power-on reset ensures that the laser is off until supply voltage has reached a specified threshold (2.55v). after power-on reset, bias current and modulation cur- rent ramp up slowly to avoid an overshoot. in the case of a por, all registers are reset to their default values. bias current monitor current out of the bmon pin is typically 1/16th the value of i bias . a resistor to ground at bmon sets the voltage gain. an internal comparator latches a soft fault if the voltage on bmon exceeds the value of v cc - 0.55v. vcsel current limiter to ensure an enhanced eye safety, an external analog vcsel current limitation can be used in addition to the digital one. an external resistor at bmax and mmax limits the maximum bias and modulation currents, respectively. a hard fault condition is latched if the vcsel current exceeds this threshold. eye safety and output control circuitry the safety and output control circuitry contains a dis- able pin (disable) and disable bit (tx_en), along with a fault indicator and fault detectors (figure 3). the MAX3798 has two types of faults, hard fault and soft fault. a hard fault triggers the fault pin and the output to the vcsel is disabled. a soft fault operates more like a warning and the outputs are not disabled. both types of faults are stored in the txstat1 and txstat2 registers. the fault pin is a latched output that can be cleared by toggling the disable pin. toggling the disable pin also clears the txstat1 and txstat2 registers. a single- point fault can be a short to v cc or gnd. table 3 shows the circuit response to various single-point failures. MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 17
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 18 ______________________________________________________________________________________ <0> <1> 0.72v <2> 0.8v <3> 1.5v <4> <5> <6> <7> por v cc - 0.65v v cc - 0.65v v cc - 0.55v fault fault register tx_stat1 <1> <0> unused tx_los bias increment biasmax mod increment modmax loss-of-signal circuit <2> <3> warning register tx_stat2 addr7 v cct v cct tout- tout+ i mod i bias i bias 16 bias v cct disable bmax 8k v cct mmax bmon reset por fault register tx_stat1 figure 3. eye safety circuitry
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 19 pin name short to v cc short to gnd open 1 los normal (note 1) normal (note 1) normal (note 1) 2 msel normal (note 1) normal (note 1) normal (note 1) 3 v ccr normal disabledhard fault (external supply shorted) (note 2) normal (note 3)redundant path 4 rout+ normal (note 1) normal (note 1) normal (note 1) 5 rout- normal (note 1) normal (note 1) normal (note 1) 6 v ccr normal disabledhard fault (external supply shorted) (note 2) normal (note 3)redundant path 7 v ccd normal disabledhard fault disabledhard fault 8 disable disabled normal (note 1). can only be disabled with other means. disabled 9 scl normal (note 1) normal (note 1) normal (note 1) 10 sda normal (note 1) normal (note 1) normal (note 1) 11 csel normal (note 1) normal (note 1) normal (note 1) 12 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 13 tin+ soft fault soft fault normal (note 1) 14 tin- soft fault soft fault normal (note 1) 15 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 16 bmon disabledhard fault normal (note 1) disabledhard fault 17 v eet disabledfault (external supply shorted) (note 2) normal disabledhard fault 18 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 19 tout- i mod is reduced disabledhard fault i mod is reduced 20 tout+ i mod is reduced disabledhard fault i mod is reduced 21 v cct normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path 22 bias i bias is onno fault disabledhard fault disabledhard fault 23 fault normal (note 1) normal (note 1) normal (note 1) 24 bmax normal (note 1) disabledhard fault disabledhard fault 25 mmax normal (note 1) disabledhard fault disabledhard fault 26 v eer disabledfault (external supply shorted) (note 2) normal normal (note 3)redundant path 27 v ccr normal disabledhard fault (external supply shorted) (note 2) normal (note 3)redundant path 28 rin- normal (note 1) normal (note 1) normal (note 1) 29 rin+ normal (note 1) normal (note 1) normal (note 1) 30 v ccr normal disabledfault (external supply shorted) (note 2) normal (note 3)redundant path table 3. circuit response to single-point faults
MAX3798 3-wire digital communication the MAX3798 implements a proprietary 3-wire digital interface. an external controller generates the clock. the 3-wire interface consists of an sda bidirectional data line, an scl clock signal input, and a csel chip-select input (active high). the external master initiates a data transfer by asserting the csel pin. the master starts to generate a clock signal after the csel pin has been set to 1. all data transfers are most significant bit (msb) first. protocol each operation consists of 16-bit transfers (15-bit address/data, 1-bit rwn). the bus master generates 16 clock cycles to scl. all operations transfer 8 bits to the MAX3798. the rwn bit determines if the cycle is read or write. see table 4. register addresses the MAX3798 contains 17 registers available for pro- gramming. table 5 shows the registers and addresses. write mode (rwn = 0) the master generates 16 clock cycles at scl in total. the master outputs a total of 16 bits (msb first) to the sda line at the falling edge of the clock. the master closes the transmission by setting csel to 0. figure 4 shows the interface timing. read mode (rwn = 1) the master generates 16 clock cycles at scl in total. the master outputs a total of 8 bits (msb first) to the sda line at the falling edge of the clock. the sda line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at the rising edge of the clock. the master closes the transmission by set- ting csel to 0. figure 4 shows the interface timing. mode control normal mode allows read-only instruction for all regis- ters except modinc and biasinc. the modinc and biasinc registers can be updated during normal mode. doing so speeds up the laser control update through the 3-wire interface by a factor of two. the nor- mal mode is the default mode. setup mode allows the master to write unrestricted data into any register except the status (txstat1, txstat2, and rxstat) registers. to enter the setup mode, the modectrl register (address = h0x0e) must be set to h0x12. after the modectrl register has been set to h0x12, the next operation is unrestricted. the setup mode is automatically exited after the next operation is finished. this sequence must be repeated if further unrestricted settings are necessary. 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 20 ______________________________________________________________________________________ pin name short to v cc short to gnd open 31 caz2 normal (note 1) normal (note 1) normal (note 1) 32 caz1 (v eer ) disabledfault (external supply shorted) (note 2) normal (note 3)redundant path normal (note 3)redundant path table 3. circuit response to single-point faults (continued) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register address rwn data that is written or read. table 4. digital communication word structure *exposed pad (connected to gnd). note 1: normaldoes not affect laser power. note 2: supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is collapsed by the short. note 3: normal in functionality, but performance could be affected. warning: shorted to v cc or shorted to ground on some pins can violate the absolute maximum ratings .
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 21 address name function h0x00 rxctrl1 receiver control register 1 h0x01 rxctrl2 receiver control register 2 h0x02 rxstat receiver status register h0x03 set_cml output cml level setting register h0x04 set_los los threshold level setting register h0x05 txctrl transmitter control register h0x06 txstat1 transmitter status register 1 h0x07 txstat2 transmitter status register 2 h0x08 set_ibias bias current setting register h0x09 set_imod modulation current setting register h0x0a imodmax maximum modulation current setting register h0x0b ibiasmax maximum bias current setting register h0x0c modinc modulation current increment setting register h0x0d biasinc bias current increment setting register h0x0e modectrl mode control register h0x0f set_pwctrl transmitter pulse-width control register h0x10 set_txde transmitter deemphasis control register table 5. register descriptions and addresses csel scl sda csel scl sda 12345678 a6 9 101112131415 0 123456789101112131415 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ch t cl t ds t dh t ch t cl t ds t d t dh t t t t figure 4. timing for 3-wire digital interface
MAX3798 register descriptions receiver control register 1 (rxctrl1) bit 3: cazx. when cazx is set to 0, no external capacitor is required (caz1 and caz2). when cazx is set to 1, an external capacitor with a minimum value of 2nf is required between caz1 and caz2. 0 = no capacitor 1 = capacitor connected bit 2: gmen. allows faster switching between data paths. 0 = disabled 1 = enabled bit 1: mode_sel. mode_sel combined with the msel pin through a logic-or function selects between the high- gain mode (1.0625gbps to 8.5gbps) or high-bandwidth mode (1.0625gbps to 10.32gbps). logic-or output 0 = high-gain mode logic-or output 1 = high-bandwidth mode bit 0: slew_rate. controls the slew rate of the output stage to reduce the effects of emi at slower data rates. effective when mode_sel = 0 and mode = gnd only. 0 = 50ps 1 = 30ps receiver control register 2 (rxctrl2) bit 6: los_en. controls the los circuitry. when rx_en is set to 0 the los detector is also disabled. 0 = disabled 1 = enabled bit 5: los_pol. controls the output polarity of the los pin. 0 = inverse 1 = normal bit 4: rx_pol. controls the polarity of the receiver signal path. 0 = inverse 1 = normal bit 3: sq_en: when sq_en = 1, the los controls the output circuitry. 0 = disabled 1 = enabled 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 22 ______________________________________________________________________________________ bit # 7 6 5 4 3 2 1 0 address name x x x x cazx gmen mode_sel slew_rate default value x x x x 1 1 0 0 h0x00 bit # 7 6 5 4 3 2 1 0 address name x los_en los_pol rx_pol sq_en rx_en rxde_en az_en default value x 1 1 1 0 1 0 1 h0x01
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 23 bit 2: rx_en. enables or disables the receive circuitry. 0 = disabled 1 = enabled bit 1: rxde_en. enables or disables the deemphasis on the receiver output. 0 = disabled 1 = enabled bit 0: az_en. enables or disables the autozero circuitry. when rx_en is set to 0, the autozero circuitry is also disabled. 0 = disabled 1 = enabled receiver status register (rxstat) bit 0: los. copy of the los output circuitry. this is a sticky bit, which means that it is cleared on a read. the first 0- to-1 transition gets latched until the bit is read by the master or por occurs. output cml level setting register (set_cml) bits 7 to 0: set_cml[7:0]. the set_cml register is an 8-bit register that can be set to range from 0 to 255, corre- sponding from 40mv p-p to 1200mv p-p . see the typical operating characteristics section for a typical cml output voltage vs. dac code graph. los threshold level setting register (set_los) bits 5 to 0: set_los[5:0]. the set_los register is a 6-bit register used to program the los threshold. see the typical operating characteristics section for a typical los threshold voltage vs. dac code graph. bit # 7 6 5 4 3 2 1 0 (sticky) address name x x x x x x x los default value x x x x x x x x h0x02 bit # 7 6 5 4 3 2 1 0 address name set_cml[7] (msb) set_cml[6] set_cml[5] set_cml[4] set_cml[3] set_cml[2] set_cml[1] set_cml[0] (lsb) default value 0 1 0 1 0 0 1 1 h0x03 bit # 7 6 5 4 3 2 1 0 address name x x set_los[5] (msb) set_los[4] set_los[3] set_los[2] set_los[1] set_los[0] (lsb) default value x x 0 0 1 1 1 0 h0x04
MAX3798 transmitter control register (txctrl) bit 3: txde_en. enables or disables the transmit output deemphasis circuitry. 0 = disabled 1 = enabled bit 2: softres. resets all registers to their default values. 0 = normal 1 = reset bit 1: tx_pol. controls the polarity of the transmit signal path. 0 = inverse 1 = normal bit 0: tx_en. enables or disables the transmit circuitry. 0 = disabled 1 = enabled transmitter status register 1 (txstat1) bit 7: fst[7]. when the v cct supply voltage is below 2.45v, the por circuitry reports a fault. once the v cct supply voltage is above 2.55v, the por resets all registers to their default values and the fault is cleared. bit 6: fst[6]. when the voltage at bmon is above v cc - 0.55v, a soft fault is reported. bit 5: fst[5]. when the voltage at mmax goes below v cc - 0.65v, a hard fault is reported. bit 4: fst[4]. when the voltage at bmax goes below v cc - 0.65v, a hard fault is reported. bit 3: fst[3]. when the common-mode voltage at v tout +/- goes below 1.5v, a soft fault is reported. bit 2: fst[2]. when the voltage at v tout +/- goes below 0.8v, a hard fault is reported. bit 1: fst[1]. when the bias voltage goes below 0.44v, a hard fault is reported. bit 0: tx_fault. copy of a fault signal in fst[7] to fst[1]. a por resets fst[7:1] to 0. transmitter status register 2 (txstat2) bit 3: imoderr. when the modulation-incremented result is greater than imodmax, a soft fault is reported. (see the programming modulation current section.) 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 24 ______________________________________________________________________________________ bit # 7 (sticky) 6 (sticky) 5 (sticky) 4 (sticky) 3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) address name fst[7] fst[6] fst[5] fst[5] fst[3] fst[2] fst[1] tx_fault default value x x x x x x x x h0x06 bit # 7 6 5 4 3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) address name x x x x imoderr ibiaserr txed x default value x x x x x x x x h0x07 bit # 7 6 5 4 3 2 1 0 address name x x x x txde_en softres tx_pol tx_en default value x x x x 0 0 1 1 h0x05
bit 2: ibiaserr. when the bias incremented result is greater than ibiasmax, then a soft fault is reported. (see the programming bias current section.) bit 1: txed. this only indicates the absence of an ac signal at the transmit input. this is not an los indicator. bias current setting register (set_ibias) bits 7 to 0: set_ibias[8:1]. the bias current dac is controlled by a total of 9 bits. the set_ibias[8:1] bits are used to set the bias current with even denominations from 0 to 510 bits. the lsb (set_ibias[0]) bit is controlled by the biasinc register and is used to set the odd denominations in the set_ibias[8:0]. modulation current setting register (set_imod) bits 7 to 0: set_imod[8:1]. the modulation current dac is controlled by a total of 9 bits. the set_imod[8:1] bits are used to set the modulation current with even denominations from 0 to 510 bits. the lsb (set_imod[0]) bit is controlled by the modinc register and is used to set the odd denominations in the set_imod[8:0]. maximum modulation current setting register (imodmax) bits 7 to 0: imodmax[7:0]. the imodmax register is an 8-bit register that can be used to limit the maximum modu- lation current. imodmax[7:0] is continuously compared to the set_imod[8:1]. maximum bias current setting register (ibiasmax) bits 7 to 0: ibiasmax[7:0]. the ibiasmax register is an 8-bit register that can be used to limit the maximum bias current. ibiasmax[7:0] is continuously compared to the set_ibas[8:1]. MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 25 bit # 7 6 5 4 3 2 1 0 address name set_ibias [8] (msb) set_ibias [7] set_ibias [6] set_ibias [5] set_ibias [4] set_ibias [3] set_ibias [2] set_ibias [1] default value 0 0 0 0 0 1 0 0 h0x08 bit # 7 6 5 4 3 2 1 0 address name set_imod [8] (msb) set_imod [7] set_imod [6] set_imod [5] set_imod [4] set_imod [3] set_imod [2] set_imod [1] default value 0 0 0 1 0 0 1 0 h0x09 bit # 7 6 5 4 3 2 1 0 address name imodmax [7] (msb) imodmax [6] imodmax [5] imodmax [4] imodmax [3] imodmax [2] imodmax [1] imodmax [0] (lsb) default value 0 0 1 1 0 0 0 0 h0x0a bit # 7 6 5 4 3 2 1 0 address name ibiasmax [7] (msb) ibiasmax [6] ibiasmax [5] ibiasmax [4] ibiasmax [3] ibiasmax [2] ibiasmax [1] ibiasmax [0] (lsb) default value 0 0 0 1 0 0 1 0 h0x0b
MAX3798 modulation current increment setting register (modinc) bit 7: set_imod[0]. this is the lsb of the set_imod[8:0] bits. this bit can only be updated by the use of modinc[4:0]. bit 5: de_inc. when this bit is set to 1 and the deemphasis on the transmit output is enabled, the set_txde[3:0] is incremented or decremented by 1 lsb. the increment or decrement is determined by the sign bit of the modinc[4:0] string of bits. bits 4 to 0: modinc[4:0]. this string of bits is used to increment or decrement the modulation current. when written to, the set_imod[8:0] bits are updated. modinc[4:0] are a twos complement string. bias current increment setting register (biasinc) bit 7: set_ibias[0]. this is the lsb of the set_ibias[8:0] bits. this bit can only be updated by the use of biasinc[4:0]. bits 4 to 0: biasinc[4:0]. this string of bits is used to increment or decrement the bias current. when written to, the set_ibias[8:0] bits are updated. biasinc[4:0] are a twos complement string. mode control register (modectrl) bits 7 to 0: modectrl[7:0]. the modectrl register enables a switch between normal and setup modes. the setup mode is achieved by setting this register to h0x12. modectrl must be updated before each write operation. exceptions are modinc and biasinc, which can be updated in normal mode. transmitter pulse-width control register (set_pwctrl) bits 3 to 0: set_pwctrl[3:0]. this is a 4-bit register used to control the eye crossing by adjusting the pulse width. 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 26 ______________________________________________________________________________________ bit # 7 6 5 4 3 2 1 0 address name set_imod [0] x de_inc modinc[4] (msb) modinc[3] modinc[2] modinc[1] modinc[0] (lsb) default value 0 0 0 0 0 0 0 0 h0x0c bit # 7 6 5 4 3 2 1 0 address name set_ibias [0] x x biasinc[4] (msb) biasinc[3] biasinc[2] biasinc[1] biasinc[0] (lsb) default value 0 0 0 0 0 0 0 0 h0x0d bit # 7 6 5 4 3 2 1 0 address name modectrl [7] msb) modectrl [6] modectrl [5] modectrl [4] modectrl [3] modectrl [2] modectrl [1] modectrl [0] (lsb) default value 0 0 0 0 0 0 0 0 h0x0e bit # 7 6 5 4 3 2 1 0 address name x x x x set_ pwctrl[3] (msb) set_ pwctrl[2] set_ pwctrl[1] set_ pwctrl[0] (lsb) default value x x x x 0 0 0 0 h0x0f
design procedure programming bias current 1) ibiasmax[7:0] = maximum_bias_current_value 2) set_ibias i [8:1] = initial _bias_current_value note: the total bias current value is calculated using the set_ibias[8:0] register. set_ibias[8:1] are the bits that can be manually written. set_ibias[0] can only be updated using the biasinc[7:0] register. when implementing an apc loop it is recommended to use the biasinc[7:0] register, which guarantees the fastest bias current update. 3) biasinc i [4:0] = new_increment_value 4) if (set_ibias i [8:1] ibiasmax[7:0]), then (set_ibias i [8:0] = set_ibias i-1 [8:0] + biasinc i [4:0]) 5) else (set_ibias i [8:0] = set_ibias i-1 [8:0]) the total bias current can be calculated as follows: 6) i bias = [set_ibias i [8:0] + 20] x 40a programming modulation current 1) imodmax[7:0] = maximum_modulation_current_value 2) set_imod i [8:1] = initial _modulation_current_value note: the total modulation current value is calculated using the set_imod[8:0] register. set_imod[8:1] are the bits that can be manually written. set_imod[0] can only be updated using the modinc[7:0] register. when implementing modulation compensation, it is rec- ommended to use the modinc[7:0] register, which guarantees the fastest bias current update. 3) modinc i [4:0] = new_increment_value 4) if (set_imod i [8:1] imodmax[7:0]), then (set_imod i [8:0] = set_imod i-1 [8:0] + modinc i [4:0]) 5) else (set_imod i [8:0] = set_imod i-1 [8:0]) the following equation is valid with assumption of 100 on-chip and 100 external differential load (rextd). the maximum value that can be set for set_txde[3:0] = 11. 6) i mod(rextd=100 ) = [(20 + set_imod i [8:0]) x 40a] for general rextd, the modulation current that is achieved using the same setting of set_imod i [8:0] as for rextd = 100 is shown below. it can be written as a function of i mod(rextd=100 ) , still assuming a 100 on- chip load. 7) programming los threshold los th = (set_los[7:0] x 1.5mv p-p ) programming transmit output deemphasis the txde_en bit must be set to 1 to enable the deem- phasis function. the set_txde register value is used to set the amount of deemphasis, which is a percent- age of the modulation current. deemphasis percentage is determined as: where the maximum set_txde[3:0] = 11. for an i mod value of 10ma, the maximum achievable deemphasis value is approximately 20%. maximum deemphasis achievable for full i mod range of 12ma is limited to 15%. with deemphasis enabled, the value of the modulation current amplitude is reduced by the calculated deem- phasis percentage. to maintain the modulation current amplitude constant, the set_imod[8:0] register must be increased by the deemphasis percentage. if the sys- tem conditions like temperature, required i mod value, etc., change during the transmit operation, the deem- phasis setting might need to be readjusted. for such an de set txde (%) _[:] = + () 100 2 3 0 64 ii xt xt mod xtd mod xtd (re ) (re ) re re = + ? = 2 100 100 ? ? ? ? ? ? ? + ? ? ? ? ? ? _[:] 1 230 64 set txde transmitter deemphasis control register (set_txde) bits 3 to 0: set_txde[3:0]. this is a 4-bit register used to control the amount of deemphasis on the transmitter out- put. when calculating the total modulation current, the amount of deemphasis must be taken into account. the deemphasis is set as a percentage of modulation current. MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 27 bit # 7 6 5 4 3 2 1 0 address name x x x x set_txde [3] (msb) set_txde [2] set_txde [1] set_txde [0] (lsb) default value x x x x 0 0 0 0 h0x10
MAX3798 impromptu deemphasis adjustment, it is recommended that the de_inc (modinc[5]) bit is used. use of this bit increments or decrements the deemphasis code setting by 1 lsb based on the sign of increment in the modinc[4:0] and, hence, the set_imod[8:0] setting. this helps maintain the ber while having the flexibility to improve signal quality by adjusting deemphasis while the transmit operation continues. this feature enables glitchless deemphasis adjustment while maintaining excellent ber performance. programming pulse-width control the eye crossing at the tx output can be adjusted using the set_pwctrl register. table 6 shows these settings. the sign of the number specifies the direction of pulse- width distortion. the code of 1111 corresponds to a balanced state for differential output. the pulse-width distortion is bidirectional around the balanced state (see the typical operating characteristics section). programming cml output settings amplitude of the cml output stage is controlled by an 8-bit dac register (set_cml). the differential output amplitude range is from 40mv p-p up to 1200mv p-p with 4.6mv p-p resolution (assuming an ideal 100 differen- tial load). output voltage r out (mv p-p ) = 40 + 4.55 (set_cml) select the coupling capacitor for ac-coupling, the coupling capacitors c in and c out should be selected to minimize the receivers deterministic jitter. jitter is decreased as the input low- frequency cutoff (f in ) is decreased. f in = 1/[2 (50)(c in )] the recommended c in and c out is 0.1f for the MAX3798. select the offset-correction capacitor the capacitor between caz1 and caz2 determines the time constant of the signal path dc-offset cancellation loop. to maintain stability, it is important to keep at least a one-decade separation between f in and the low-frequency cutoff (f oc ) associated with the dc-off- set cancellation circuit. a 1nf capacitor between caz1 and caz2 is recommended for the MAX3798. applications information layout considerations to minimize inductance, keep the connections between the MAX3798 output pins and laser diode as close as possible. optimize the laser diode performance by placing a bypass capacitor as close as possible to the laser anode. use good high-frequency layout tech- niques and multiple-layer boards with uninterrupted ground planes to minimize emi and crosstalk. exposed-pad package the exposed pad on the 32-pin tqfn provides a very low-thermal resistance path for heat removal from the ic. the pad is also electrical ground on the MAX3798 and must be soldered to the circuit board ground for proper thermal and electrical performance. refer to application note 862: hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. laser safety and iec 825 using the MAX3798 laser driver alone does not ensure that a transmitter design is compliant with iec 825. the entire transmitter circuit and component selections must be considered. each user must determine the level of fault tolerance required by the application, rec- ognizing that maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application in which the failure of a maxim product could create a situation where personal injury or death could occur. 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 28 ______________________________________________________________________________________ set_pwcrtl[3:0] pwd set_pwcrtl[3:0] pwd 1000 -7 0111 8 1001 -6 0110 7 1010 -5 0101 6 1011 -4 0100 5 1100 -3 0011 4 1101 -2 0010 3 1110 -1 0001 2 1111 0 0000 1 table 6. eye-crossing settings for set_pwcrtl
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 29 register function/ address register name normal mode setup mode bit number /type bit name default value notes r rw 3 cazx 1 external autozero capacitor 0: disconnected, 1: connected r rw 2 gmen 1 mode-select switching time boost 0: off, 1: on r rw 1 mode_sel 0 mode-select 0: high-gain mode, 1: high- bandwidth mode receiver control register 1 address = h0x00 rxctrl1 r rw 0 slew_rate 0 slew-rate select 0: slow mode, 1: fast mode r rw 6 los_en 1 los control 0: disable, 1: enable (always 0 when rx_en = 0) r rw 5 los_pol 1 los polarity 0: inverse, 1: normal r rw 4 rx_pol 1 rx polarity 0: inverse, 1: normal r rw 3 sq_en 0 squelch 0: disable, 1: enable r rw 2 rx_en 1 rx control 0: disable, 1: enable r rw 1 rxde_en 0 rx deemphasis 0: disable, 1: enable receiver control register 2 address = h0x01 rxctrl2 r rw 0 az_en 1 rx autozero control 0: disable, 1: enable (always 0 when rx_en = 0) receiver status register address = h0x02 rxstat r r 0 (sticky) los x copy of los output signal r rw 7 set_cml[7] 0 msb output level dac r rw 6 set_cml[6] 1 r rw 5 set_cml[5] 0 r rw 4 set_cml[4] 1 r rw 3 set_cml[3] 0 r rw 2 set_cml[2] 0 r rw 1 set_cml[1] 1 output cml level setting register address = h0x03 set_cml r rw 0 set_cml[0] 1 lsb output level dac table 7. register summary
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 30 ______________________________________________________________________________________ register function/ address register name normal mode setup mode bit number /type bit name default value notes r rw 5 set_los[5] 0 msb los threshold dac r rw 4 set_los[4] 0 r rw 3 set_los[3] 1 r rw 2 set_los[2] 1 r rw 1 set_los[1] 0 los threshold level setting register address = h0x04 set_los r rw 0 set_los[0] 0 lsb los threshold dac r rw 3 txde_en 0 tx deemphasis 0: disable, 1: enable r rw 2 softres 0 global digital reset r rw 1 tx_pol 1 tx polarity 0: inverse, 1: normal transmitter control register address = h0x05 txctrl r rw 0 tx_en 1 tx control 0: disable, 1: enable r r 7 (sticky) fst[7] x tx_por tx_vcc low- limit violation r r 6 (sticky) fst[6] x bmon open/shorted to v cc r r 5 (sticky) fst[5] x mmax current exceeded or open/shorted to gnd r r 4 (sticky) fst[4] x bmax current exceeded or open/shorted to gnd r r 3 (sticky) fst3] x v tout +/- common-mode low-limit violation r r 2 (sticky) fst[2] x v tout +/- low-limit violation r r 1 (st ic ky) fst[1] x bias open or shorted to gnd transmitter status register 1 address = h0x06 txstat1 r r 0 (sticky) tx_fault x copy of fault signal in case por bits 6 to 1 reset to 0 r r 3 (sticky) imoderr x warning increment result > imodmax r r 2 (sticky) ibiaserr x warning increment result > ibiasmax r r 1 (sticky) txed x tx edge detection transmitter status register 2 address = h0x07 txstat2 r r 0 (sticky) unused x unused table 7. register summary (continued)
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 31 register function/ address register name normal mode setup mode bit number /type bit name default value notes r rw 8 set_ibias[8] 0 msb bias dac r rw 7 set_ibias[7] 0 r rw 6 set_ibias[6] 0 r rw 5 set_ibias[5] 0 r rw 4 set_ibias[4] 0 r rw 3 set_ibias[3] 1 r rw 2 set_ibias[2] 0 r rw 1 set_ibias[1] 0 bias current setting register address = h0x08 set_ibias accessible through reg_addr = 13 0 set_ibias[0] 0 lsb bias dac r rw 8 set_imod[8] 0 msb modulation dac r rw 7 set_imod[7] 0 r rw 6 set_imod[6] 0 r rw 5 set_imod[5] 1 r rw 4 set_imod[4] 0 r rw 3 set_imod[3] 0 r rw 2 set_imod[2] 1 r rw 1 set_imod[1] 0 modulation current setting register address = h0x09 set_imod accessible through reg_addr = 12 0 set_imod[0] 0 lsb modulation dac r rw 7 imodmax[7] 0 msb modulation limit r rw 6 imodmax[6] 0 r rw 5 imodmax[5] 1 r rw 4 imodmax[4] 1 r rw 3 imodmax[3] 0 r rw 2 imodmax[2] 0 r rw 1 imodmax[1] 0 maximum modulation current setting register address = h0x0a imodmax r rw 0 imodmax[0] 0 lsb modulation limit r rw 7 ibiasmax[7] 0 msb bias limit r rw 6 ibiasmax[6] 0 r rw 5 ibiasmax[5] 0 r rw 4 ibiasmax[4] 1 r rw 3 ibiasmax[3] 0 r rw 2 ibiasmax[2] 0 r rw 1 ibiasmax[1] 1 maximum bias current setting register address = h0x0b ibiasmax r rw 0 ibiasmax[0] 0 lsb bias limit table 7. register summary (continued)
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 32 ______________________________________________________________________________________ register function/ address register name normal mode setup mode bit number /type bit name default value notes r r 7 set_imod[0] 0 lsb of set_imod dac register address = h0x09 r r 6 x 0 r r 5 de_inc 0 deemphasis increment 0: no update, 1: set_txde updates 1 lsb rw rw 4 modinc[4] 0 msb mod dac twos complement rw rw 3 modinc[3] 0 rw rw 2 modinc[2] 0 rw rw 1 modinc[1] 0 modulation current increment setting register address = h0x0c modinc rw rw 0 modinc[0] 0 lsb mod dac twos complement r r 7 set_ibias[0] 0 lsb of set_ibias dac register address = h0x08 r r 6 x 0 r r 5 x 0 rw rw 4 biasinc[4] 0 msb bias dac twos complement rw rw 3 biasinc[3] 0 rw rw 2 biasinc[2] 0 rw rw 1 biasinc[1] 0 bias current increment setting register address = h0x0d biasinc rw rw 0 biasinc[0] 0 lsb bias dac twos complement rw rw 7 modectrl[7] 0 msb mode control rw rw 6 modectrl[6] 0 rw rw 5 modectrl[5] 0 rw rw 4 modectrl[4] 0 rw rw 3 modectrl[3] 0 rw rw 2 modectrl[2] 0 rw rw 1 modectrl[1] 0 mode control register address = h0x0e modectrl rw rw 0 modectrl[0] 0 lsb mode control r rw 3 set_pwctrl[3] 0 msb tx pulse-width control r rw 2 set_pwctrl[2] 0 r rw 1 set_pwctrl[1] 0 transmitter pulse- width control register address = h0x0f set_ pwctrl r rw 0 set_pwctrl[0] 0 lsb tx pulse-width control r rw 3 set_txde[3] 0 msb tx deemphasis r rw 2 set_txde[2] 0 r rw 1 set_txde[1] 0 transmitter deemphasis control register address = h0x10 set_txde r rw 0 set_txde[0] 0 lsb tx deemphasis table 7. register summary (continued)
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver ______________________________________________________________________________________ 33 50 50 50 50 v ccr v ccr v eer v eer rin+ rout+ rout- rin- 50 75k 50 v cct v ccd v eet v eed tin+ tin- sda 50 50 v cct v eet tout+ tout- deemphasis control deemphasis control 8k v cct v eet disable 376 v eet fault, los 75k v ccd v eed scl, csel 75k v ccr v eer msel clamp control loop control loop figure 5. simplified i/o structures
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver 34 ______________________________________________________________________________________ MAX3798 los rout+ rout- msel disable fault ep v eet v ccr caz1 caz2 v eer 0.1 f 0.1 f 1nf 0.1 f rin+ rin- v cct bias tout- scl v ccd csel sda 0.1 f 4.7 r mon i mon 10g pin flex rosa 10g vcsel flex tosa 3-wire interface receiver transmitter 0.1 f tout+ mmax 0.1 f vsel +3.3v +3.3v sfp optical transceiver sfp connector host board vcc_rx vcc_tx md 400 bmax bmon 400 +3.3v +3.3v +3.3v 4.7 +3.3v 3-wire interface adc i 2 c sfp+ controller i mon mode_def2 (sd) mode_def1 (sclk) tx_disable tx_fault 2k r pd supply filter host filter supply filter host filter z diff = 100 tin+ tin- 0.1 f 0.1 f z diff = 100 serdes typical application circuit
MAX3798 1.0625gbps to 10.32gbps, integrated, low- power sfp+ limiting amplifier and vcsel driver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. thin qfn (5mm ) top view *the exposed pad must be connected to ground. 29 30 28 27 12 11 13 msel rout+ rout- v ccr v ccd 14 los fault v cct tout+ bmax tout- v cct 12 rin- 4567 23 24 22 20 19 18 rin+ v ccr tin- tin+ v cct csel v ccr bias 3 21 31 10 caz2 sda 32 9 caz1 scl v ccr 26 15 v cct v eer 25 16 bmon disable v eet 8 17 mmax MAX3798 *ep + pin configuration chip information process: sige bipolar package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 32 tqfn-ep t3255+3 21-0140

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